View M13S128324A-2M_8511429.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 1/48 ddr sdram 1m x 32 bit x 4 banks double data rate sdram features z double-data-rate architecture, two data transfers per clock cycle z bi-directional data strobe (dqs) z differential clock inputs (clk and clk ) z dll aligns dq and dqs transition with clk transition z quad bank operation z cas latency : 2, 2.5, 3 z burst type : sequential and interleave z burst length : 2, 4, 8 z all inputs except data & dm are sampled at the rising edge of the system clock(clk) z data i/o transitions on both edges of data strobe (dqs) z dqs is edge-aligned with data for reads; center-aligned with data for writes z data mask (dm) for write masking only z v dd = 2.375v ~ 2.625v, v ddq = 2.375v ~ 2.625v z v dd = 2.5v ~ 2.7v, v ddq = 2.5v ~ 2.7v (for speed -3.6) z auto & self refresh z 32ms refresh period (4k cycle) z 2.5v i/o (sstl_2 compatible) ordering information product id max freq. v dd package comments m13s128324a -3.6bg2m 275mhz (ddr550) 2.6v m13s128324a -4bg2m 250mhz (ddr500) 2.5v m13s128324a -5bg2m 200mhz (ddr400) 2.5v m13s128324a -6bg2m 166mhz (ddr333) 2.5v 144 ball fbga pb-free
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 2/48 functional block diagram clk, clk bank a command decoder control logic latch circuit bank b dm dq mode register & extended mode register column address buffer & refresh counter row address buffer & refresh counter row decoder sense amplifier column decoder data control circuit input & output buffer address, ba clock generator clk clk cke cs ras cas we dll dqs bank c bank d
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 3/48 ball configuration (top view) (bga144, 12mmx12mmx1.4mm body, 0.8mm ball pitch) dqs0 vss thermal dq4 dq6 dq7 dq17 dq19 dqs2 dq21 dq22 cas cs ras dm0 vddq dq5 vddq dq16 dq18 dm2 dq20 dq23 we nc nc vssq nc vssq vdd vddq vddq nc vddq vddq vdd ba0 nc dq3 vddq vssq vss vssq vss a0 ba1 23456789 vssq vssq vssq vssq dq2 dq1 vssq vssq vss a10 a1 a2 dq0 vddq vdd vss vss vdd a3 a11 dq31 vddq vdd vss a4 a9 dq29 dq30 vssq vssq nc a6 a5 vss vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss vdd vss thermal vss thermal vss thermal vss thermal 10 dq28 vddq vssq vss vss a7 nc vssq nc vssq vdd vdd a8/ap clk dm3 vddq dq26 vddq cke clk dqs3 dq27 dq25 dq24 nc vref nc dq8 vddq nc dq15 dq13 dm1 dq11 dq9 nc dq14 dq12 dqs1 dq10 vssq vssq vssq vssq vssq 11 12 vddq vddq vddq 13 b c d e f g h j k l m n pin description pin name function pin name function a0~a11, ba0,ba1 address inputs - row address a0~a11 - column address a0~a7 a8/ap : auto precharge ba0, ba1 : bank selects (4 banks) dm0~dm3 dm is an input mask sign al for write data. dm0 corresponds to the data on dq0~dq7; dm1 corresponds to the data on dq8~dq15; dm2 corresponds to the data on dq16~dq23; dm3 corresponds to the data on dq24~dq31. dq0~dq31 data-in/data-out clk, clk clock input ras row address strobe cke clock enable cas column address strobe cs chip select we write enable v ddq supply voltage for dq v ss ground v ssq ground for dq v dd power v ref reference voltage for sstl_2 dqs0~dqs3 (for fbga) bi- directional data strobe. dqs0 correspond to the data on dq0~dq7; dqs1 correspond to the data on dq8~dq15; dqs2 correspond to the data on dq16~dq23; dqs3 correspond to the data on dq24~dq31. nc no connection
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 4/48 absolute maximum rating parameter symbol value unit voltage on v dd & v ddq supply relative to v ss v dd , v ddq -1.0 ~ 3.6 v voltage on inputs relative to v ss v input -1.0 ~ 3.6 v voltage on i/o pins relative to v ss v io -0.5 ~ v ddq +0.5 v operating ambient temperature t a 0 ~ +70 c storage temperature t stg -55 ~ +150 c power dissipation p d 2 w short circuit current i os 50 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restrict ed to recommend operation condition. exposure to higher than recommended voltage for exten ded periods of time could affect device reliability. dc operation condition & specifications dc operation condition recommended operating conditions (voltage reference to v ss = 0v, t a = 0 to 70 c ) min max parameter symbol -3.6 -4/5/6 -3.6 -4/5/6 unit note supply voltage v dd 2.5 2.375 2.7 2.625 v i/o supply voltage v ddq 2.5 2.375 2.7 2.625 v i/o reference voltage v ref 0.49*v ddq 0.51*v ddq v 1 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v 2 input logic high voltage v ih (dc) v ref + 0.15 v ddq + 0.3 v input logic low voltage v il (dc) -0.3 v ref - 0.15 v input voltage level, clk and clk inputs v in (dc) -0.3 v ddq + 0.3 v input differential voltage, clk and clk inputs v id (dc) 0.36 v ddq + 0.6 v 3 v?i matching: pullup to pulldown cu rrent ratio vi (ratio) 0.71 1.4 - 4 input leakage current: any input 0v v in v dd (all other pins not tested under = 0v) i l -2 2 v out v ddq ) i oz -5 5
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 5/48 dc operation conditions - continued parameter symbol min max unit note output high current (full strength driver) (v out =v ddq -0.373v, min v ref , min v tt ) i oh -16.8 ma 5, 7 output low current (full strength driver) (v out = 0.373v, max v ref , max v tt ) i ol +16.8 ma 5, 7 output high current (reduced strength driver ? 60%) (v out = v ddq -0.763v, min v ref , min v tt ) i oh -9 ma 6 output low current (reduced strength driver ? 60%) (v out = 0.763v, max v ref , max v tt ) i ol +9 ma 6 output high current (reduced strength driver ? 30%) (v out = v ddq -1.056v, min v ref , min v tt ) i oh -4.5 ma 6 output low current (reduced strength driver ? 30%) (v out = 1.056v, max v ref , max v tt ) i ol +4.5 ma 6 notes: 1. v ref is expected to be equal to 0.5* v ddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% of the dc value. 2. v tt is not applied directly to the device. v tt is system supply for signal termination re sistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 3. v id is the magnitude of the difference between t he input level on clk and the input level on clk . 4. the ratio of the pullup current to the pulldown current is specified for the same temperature and voltag e, over the entire temperature and voltage range, fo r device drain to source voltages from 0.25 v to 1.0 v. for a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1. 7 for device drain to source voltages from 0.1 to 1.0. 5. v oh = 2.15v, v ol =0.35v for speed -3.5; v oh = 2.025v, v ol =0.35v for others. 6. v oh = 2.1v, v ol =0.4v for speed -3.5; v oh = 1.975v, v ol =0.4v for others. 7. the values of i oh (dc) is based on v ddq = 2.5v and v tt = 1.29v for speed -3.5; v ddq = 2.375v and v tt = 1.2275v for others. the values of i ol (dc) is based on v ddq = 2.5v and v tt = 1.21v for speed -3.5; v ddq = 2.375v and v tt = 1.1475v for others.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 6/48 idd parameters and test conditions test condition symbol note operating current (one bank active - precharge): t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles; cs = high between valid commands. idd0 operating current (one bank active - read - precharge): one bank open; bl = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per deselect cycle; cs = high between valid commands idd1 2 precharge power-down standby current: all banks idle; power-down mode; t ck = t ck (min); cke precharge floating standby current: cs v ih (min); all banks idle; cke v ih (min); t ck = t ck (min); address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs, and dm. idd2f precharge quiet standby current: cs v ih (min); all banks idle; cke v ih (min); t ck = t ck (min); address and other control inputs stable at v ih (min) or active power-down standby current: one bank active; power-down mode; cke v il (max); t ck = t ck (min); v in = v ref for dq, dqs, and dm. idd3p active standby current: cs v ih (min); cke v ih (min); one bank active; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle. idd3n operating current (burst read): bl = 2; continuous burst reads; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma; 50% of data changing on every transfer. idd4r operating current (burst write): bl = 2; continuous burst writes; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; 50% of input data changing at every transfer. idd4w auto refresh current: t rc = t rfc (min) idd5 self refresh current: cke 0.2v; external clock on; t ck = t ck (min) idd6 1 operating current (four bank operation): four-bank interleaving reads (burst = 4) with auto precharge; t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active, read, or write commands; i out = 0ma. idd7 2 notes: 1. enable on-chip refresh and address counters. 2. random address is changing; 50% of data is changing at every transfer.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 7/48 idd specifications version symbol -3.6 -4 -5 -6 unit idd0 235 210 175 145 ma idd1 245 220 190 180 ma idd2p 40 40 40 40 ma idd2f 135 120 115 95 ma idd2q 135 120 115 95 ma idd3p 60 55 50 45 ma idd3n 150 130 120 110 ma idd4r 440 400 350 300 ma idd4w 470 430 380 330 ma idd5 320 290 270 250 ma idd6 5 5 5 5 ma idd7 500 460 410 360 ma input / output capacitance (v dd = 2.375v~2.625v, v ddq =2.375v~2. 625v, t a = 25 c , f = 1mhz) (v dd = 2.5v~2.7v, v ddq =2.5v~2.7v, t a = 25 c , f = 1mhz (for speed -3.6)) parameter symbol min max unit input capacitance (a0~a11, ba0~ba1, cke, cs , ras , cas , we ) c in1 1 4 pf input capacitance (clk, clk ) c in2 1 5 pf data & dqs input/output capacitance c out 1 6.5 pf input capacitance (dm) c in3 1 6.5 pf
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 8/48 ac operation conditions & timing specifications ac operation conditions parameter symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih (ac) v ref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals v il (ac) v ref - 0.31 v input differential voltage, clk and clk inputs v id (ac) 0.7 v ddq +0.6 v 1 input crossing point voltage, clk and clk inputs v ix (ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2 notes: 1. v id is the magnitude of the difference between the input level on clk and the input on clk . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must tr ack variations in the dc level of the same. ac overshoot / undershoot specification value parameter pin -3.6/ -4/ -5 / -6 unit address, control 1.5 v maximum peak amplitude allowed for overshoot data, strobe, mask 1.2 v address, control 1.5 v maximum peak amplitude allowed for undershoot data, strobe, mask 1.2 v address, control 4.5 v-ns maximum overshoot area above v dd data, strobe, mask 2.4 v-ns address, control 4.5 v-ns maximum undershoot area below v ss data, strobe, mask 2.4 v-ns
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 9/48 ac timing parameter & specifications (note: 1~6, 9~10) -3.6 -4 -5 -6 parameter symbol min max min max min max min max unit note cl2 7.5 12 7.5 12 7.5 12 7.5 12 cl2.5 6.0 12 6.0 12 6.0 12 6.0 12 clock period cl3 t ck 3.6 12 4.0 12 5.0 12 6.0 12 ns dq output access time from clk/ clk t ac -0.6 +0.6 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns clk high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck clk low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck dqs output access time from clk/ clk t dqsck -0.6 +0.6 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns clock to first rising edge of dqs delay t dqss 0.8 1.2 0.8 1.2 0.8 1.2 0.8 1.2 t ck dq and dm input setup time (to dqs) t ds 0.4 0.45 0.45 0.45 ns dq and dm input hold time (to dqs) t dh 0.4 0.45 0.45 0.45 ns dq and dm input pulse width (for each input) t dipw 1.75 1.75 1.75 1.75 ns 18 address and control input setup time (fast slew rate) t is 0.9 0.9 1.0 1.0 ns 15,17~19 address and control input hold time (fast slew rate) t ih 0.9 0.9 1.0 1.0 ns 15,17~19 address and control input setup time (slow slew rate) t is 1.0 1.0 1.1 1.1 ns 16~19 address and control input hold time (slow slew rate) t ih 1.0 1.0 1.1 1.1 ns 16~19 control and address input pulse width (for each input) t ipw 2.2 2.2 2.2 2.2 ns 18 dqs input high pulse width t dqsh 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs input low pulse width t dqsl 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs falling edge to clk setup time t dss 0.2 0.2 0.2 0.2 t ck dqs falling edge hold time from clk t dsh 0.2 0.2 0.2 0.2 t ck data strobe edge to output data edge t dqsq 0.4 0.4 0.4 0.45 ns 22 data-out high-impedance time from clk/ clk t hz -0.7 +0.7 -0.7 +0.7 -0.7 +0 .7 -0.7 +0.7 ns 11 data-out low-impedance time from clk/ clk t lz -0.7 +0.7 -0.7 +0.7 -0.7 +0 .7 -0.7 +0.7 ns 11 clock half period t hp t cl min or t ch min t cl min or t ch min t cl min or t ch min t cl min or t ch min ns 20,21 dq-dqs output hold time from dqs t qh t hp - t qhs t hp - t qhs t hp - t qhs t hp - t qhs ns 21 data hold skew factor t qhs 0.4 0.45 0.45 0.5 ns
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 10/48 ac timing parameter & specifications - continued -3.6 -4 -5 -6 parameter symbol min max min max min max min max unit note active to precharge command t ras 39.6 70k 40 70k 40 70k 42 70k ns active to active /auto refresh command period t rc 54 52 55 60 ns auto refresh to active /auto refresh command period t rfc 64.8 68 70 72 ns active to read delay t rcdrd 14.4 15 15 18 ns active to write delay t rcdwr 10 10 10 18 ns precharge command period t rp 14.4 15 15 18 ns active to read with auto precharge command t rap t rcdrd or t ras min t rcdrd or t ras min t rcdrd or t ras min t rcdrd or t ras min ns active bank a to active bank b command t rrd 10 10 10 12 ns write recovery time t wr 15 15 15 15 ns write data in to read command delay t wtr 2 2 2 2 t ck col. address to col. address delay t ccd 1 1 1 1 t ck average periodic refresh interval t refi 7.8 7.8 7.8 7.8 us 14 write preamble t wpre 0.25 0.25 0.25 0.25 t ck write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 12 read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ck read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck clock to dqs write preamble setup time t wpres 0 0 0 0 ns 13 mode register set command cycle time t mrd 2 2 2 2 t ck exit self refresh to read command t xsrd 200 200 200 200 t ck exit self refresh to non-read command t xsnr 75 75 75 75 ns auto precharge write recovery + precharge time t dal (t wr /t ck ) +(t rp /t ck ) (t wr /t ck ) +(t rp /t ck ) (t wr /t ck ) +(t rp /t ck ) (t wr /t ck ) +(t rp /t ck ) t ck 23 notes: 1. all voltages referenced to v ss . 2. tests for ac timing, idd, and electr ical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specific ations and device operation are guaranteed for the full voltage range specified. 3. the below figure represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise repres entation of the typical system environm ent nor a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics).
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 11/48 4. ac timing and idd tests may use a v il to v ih swing of up to 1.5 v in the test envir onment, but input timing is still referenced to v ref (or to the crossing point for clk/ clk ), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1 v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e ., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 6. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke 0.2v ddq is recognized as low. 7. enables on-chip refresh and address counters. 8. idd specifications ar e tested after the device is properly initialized. 9. the clk/ clk input reference level (for timing referenced to clk/ clk ) is the point at which clk and clk cross; the input reference level for signals other than clk/ clk , is v ref . 10. the output timing reference voltage level is v tt . 11. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level but specif y when the device output is no longer driving (t hz ), or begins driving (t lz ). 12. the maximum limit for this parameter is not a device limit. the device will operate with a gr eater value for this parameter , but system performance (bus turnaround) will degrade accordingly. 13. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defined as monot onic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be tr ansitioning from high- z to logic low. if a previous write was in progress, dqs could be high, low, or transitioni ng from high to low at this time, depending on t dqss . 14. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 15. for command/address input slew rate 1.0 v/ns 16. for command/address input slew rate 0.5 v/ns and < 1.0 v/ns 17. for clk & clk slew rate 1.0 v/ns 18. these parameters guarantee device timing, but they are not necessarily tested on each device. they may be guaranteed by device design or tester correlation. 19. slew rate is measured between v oh (ac) and v ol (ac). 20. min (t cl , t ch ) refers to the smaller of the actual clock low time and t he actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ).....for example, t cl and t ch are = 50% of the period, less the half period jitter (t jit (hp)) of the clock source, and less the half period jitter due to crosstalk (t jit (crosstalk)) into the clock traces. 21. t qh = t hp - t qhs , where: t hp = minimum half clock period for any given cycle and is defined by clock high or clock low (t ch , t cl ). t qhs accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, bot h of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-chann el variation of t he output drivers. 22. t dqsq consists of data pin skew and output pattern effects, and p-channel to n-chan nel variation of the output drivers for any given cycle. 23. for each of the terms above, if not already an integer, round to the next highest integer.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 12/48 command truth table command cken-1 cken cs ras cas we dm ba0~1 a8/ap a11~a9, a7~a0 note register extended mrs h x l l l l x op code 1,2 register mode register set h x l l l l x op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h 3 refresh self refresh exit l h h x x x xx 3 bank active & row addr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge enable h x l h l h x v h column address (a0~a7) 4 auto precharge disable l 4,8 write & column address auto precharge enable h x l h l l v v h column address (a0~a7) 4,6,8 burst terminate h x l h h l x x 7 bank selection v l precharge all banks h x l l h l x x h x 5 h x x x entry h l l h h h x active power down mode exit l h x x x x x x h x x x entry h l l h h h x h x x x precharge power down mode exit l h l h h h x x deselect (nop) h x x x no operation (nop) h x l h h h xx (v = valid, x = don?t care, h = logic high, l = logic low) notes: 1. op code: operand code. a0~a11 & ba0~ba1: program keys. (@emrs/mrs) 2. emrs/mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by ?auto?. auto/self refresh can be issued onl y at all banks precharge state. 4. ba0~ba1: bank select addresses. if both ba0 and ba1 are ?low? at read, write, row active and precharge, bank a is selected. if ba0 is ?high? and ba1 is ?low? at read, writ e, row active and precharge, bank b is selected. if ba0 is ?low? and ba1 is ?high? at read, write, row active and precharge, bank c is selected. if both ba0 and ba1 are ?high? at read, write, row active and precharge, bank d is selected. 5. if a8/ap is ?high? at row precharge, ba is ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command ca n be issued after the end of burst. new row active of the associated bank can be issued at t rp after end of burst. 7. burst terminate command is valid at every burst length. 8. dm and data-in are sampled at the rising and falling edges of the dqs. data-in byte are masked if the corresponding and coincident dm is ?high?. (write dm latency is 0).
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 13/48 basic functionality power-up and initialization sequence ddr sdram must be powered up and initialized in a predefined manner. operational proc edures other than t hose specified may result in undefined operation. no power sequencing is specified during power up and power down given the following criteria: ? v dd and v ddq are driven from a single power converter output, and ? v tt is limited to 1.35 v, and ? v ref tracks v ddq /2 or, the following relationships must be followed: ? v ddq is driven after or with v dd such that v ddq < v dd + 0.3 v, and ? v tt is driven after or with v ddq such that v tt < v ddq + 0.3 v, and ? v ref is driven after or with v ddq such that v ref < v ddq + 0.3 v. at least one of these two conditions must be met. except for cke, inputs are not recognized as valid until after v ref is applied. cke is an sstl_2 input, but will detect an lvcmos low level after v dd is applied. maintaining an lvcmos low level on cke during power-up is required to guarantee that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal operation (by a read access). after all power supply and reference voltages are stabl e, and the clock is stable, the ddr sdram requires a 200 s delay prior to applying an executable command. once the 200 s delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharge all command should be applied. next a mode register set command should be issued for the extended mode register, to enable the dll, and then a mode register set command should be issued for the mode register, to reset the dll, and to program the operating parameters. 200 clo ck cycles are required between the dll res et and any executable command. a precharge all command should be applie d, placing the device in t he ?all banks idle? state. once in the idle state, two auto refr esh cycles must be performed. additionally , a mode register set command for the mode register, with the reset dll bit deactivated (i.e., to program operating parameters without resetting the dll) must be performe d. following these cycles, the ddr sdra m is ready for normal operation.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 14/48 mode register definition mode register set (mrs) the mode register stores the data for controlling the various operati ng modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dl l reset and various vendor specific options to make ddr sdram useful for variety of different applications. the default value of t he register is not defined, therefore the mode register must be written after emr s setting for proper ddr sdram operation. the mode register is written by asserting low on cs , ras , cas , we and ba0~ba1 (the ddr sdram should be in all bank precharge with cke already high prio r to writing into the mode re gister). the state of address pins a0~a11 in the same cycle as cs , ras , cas , we and ba0~ba1 going low is written in the mode register. two clock cycles are requested to complete the write operation in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a0~a2, addressing mode uses a3, cas latency (read latency from column address) uses a4~a6. a7 is used for test mode. a8 is used for dll reset. a7 must be set to low for normal m rs operation. refer to the table for specific c odes for various burst length, addressing modes and cas latencies. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address bus 0 0 rfu dll tm cas latency bt burst length mode register a8 dll reset a7 mode a3 burst type 0 no 0 normal 0 sequential 1 yes 1 test 1 interleave burst length cas latency length a6 a5 a4 latency a2 a1 a0 sequential interleave ba1 ba0 operating mode 0 0 0 reserve 0 0 0 reserve reserve 0 0 mrs cycle 0 0 1 reserve 0 0 1 2 2 0 1 emrs cycle 0 1 0 2 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 reserve 1 0 0 reserve reserve 1 0 1 reserve 1 0 1 reserve reserve 1 1 0 2.5 1 1 0 reserve reserve 1 1 1 reserve 1 1 1 reserve reserve note: rfu (reserved for future use) must stay ?0? during mrs cycle.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 15/48 extended mode register set (emrs) the extended mode register stores the data enabling or disabling dll and selecti ng output drive strength. the default value of the extended mode register is not defined, t herefore the extended mode register must be written after power up for enabling or disa bling dll. the extended mode register is written by asserting low on cs , ras , cas , we , ba1 and high on ba0 (the ddr sdram should be in all bank precharge with cke already high prior to wr iting into the extended mode regi ster). the state of address p ins a0~a11 and ba0~ba1 in the same cycle as cs , ras , cas and we going low is written in the extended mode register. two clock cycles are requested to complete t he write operation the mode regi ster. the mode register cont ents can be changed using t he same command and clock cycle requirements during operation as long as all banks are in the idle state. a0 is used for dll enabl e or disable. a1 and a6 are used for setting drive strength. ?high? on ba0 is used for emrs. all the other address pins except a0 ~1, a6 and ba0 must be set to low for proper emrs oper ation. refer to the table for specific codes. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address bus 0 1 rfu ds rfu ds dll extended mode register a6 a1 driver strength a0 dll enable 0 0 100% strength 0 enable 0 1 60% strength 1 disable 1 0 rfu 1 1 30% strength ba1 ba0 operating mode 0 0 mrs cycle 0 1 emrs cycle note: rfu (reserved for future use) must stay ?0? during emrs cycle.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 16/48 burst address ordering for burst length burst length starting address (a2, a1, a0) sequential mode interleave mode xx0 0, 1 0, 1 2 xx1 1, 0 1, 0 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 4 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 8 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 dll enable / disable the dll must be enabled for normal operation. dll enable is r equired during power-up initialization, and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluati on (upon exiting self refresh mode, the dll is enabled automatically). any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. output drive strength the normal drive strength for all outputs is specified to be sstl_2, class ii. the dev ice also support reduced drive strength options, intended for lighter load an d/or point-to-point environments. mode register 01 234 567 command t ck precharge all banks mrs / emrs t rp *2 *1 clk clk any command t mrd *1: mrs/emrs can be issued only at all banks precharge state. *2: minimum t rp is required to issue mrs/emrs command.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 17/48 precharge the precharge command is used to precharge or close a bank t hat has activated. the precharge command is issued when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank respectively or all banks simultaneously. the bank select addresses (ba0, ba1) are used to define which bank is precharged when the command is initiated. for write cycle, t wr (min) must be satisfied until the prec harge command can be issued. after t rp from the precharge, an active command to the same bank can be initiated. burst selection for precharge by bank address bits a8/ap ba1 ba0 precharge 0 0 0 bank a only 0 0 1 bank b only 0 1 0 bank c only 0 1 1 bank d only 1 x x all banks no operation & device deselect the device should be deselected by deactivating the cs signal. in this mode ddr sdram should ignore all the control inputs. the ddr sdrams are put in nop mode when cs is active and by deactivating ras , cas and we . for both deselect and nop the device should finish the current operation when this command is issued. bank / row active the bank activation command is issued by holding cas and we high with cs and ras low at the rising edge of the clock (clk). the ddr sdram has two independent banks, so bank se lect addresses (ba0, ba1) are required. the bank activation command must be applied before any read or write operation is exec uted. the bank activation command to the first read or write command must meet or exceed the minimum of ras to cas delay time (t rcdrd or t rcdwr min). once a bank has been activated, it must be precharged before another bank activation command can be applied to the same bank. the minimum time interval between interleaved bank activation command (bank a to bank b and vice versa) is the bank to bank delay time (t rrd min). bank activation command cycle ( cas latency = 3) address 01 23 command bank a row addr. bank a row. addr. bank b row addr. bank a activate nop bank b activate nop bank a activate ras-cas delay ( t rcdwr ) ras-ras delay ( t rrd ) row cycle time ( t rc ) :don'tcare clk clk nop tn tn+1 tn+2 bank a col. addr. write a with ap
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 18/48 read this command is used after the row activate command to initiate the burst read of data. the read command is initiated by activa ting cs , ras , cas , and deasserting we at the same clock rising edge as described in the command truth tabl e. the length of the burst and the cas latency time will be determined by the values programmed during the mrs command. write this command is used after the row activate command to initiate the burst write of data. the wr ite command is initiated by acti vating cs , ras , cas , and we at the same clock rising edge as describe in the command truth table. the le ngth of the burst will be determined by the values prog rammed during the mrs command. burst read operation burst read operation in ddr sdram is in the same manner as t he current sdram such that the burst read command is issued by asserting cs and cas low while holding ras and we high at the rising edge of the clock (clk) after t rcdrd from the bank activation. the address inputs determine the starting address for the burst. the mode register sets type of burst (sequential o r interleave) and burst length (2, 4, 8). the first output data is available after the cas latency from the read command, and the consecutive data are presented on the falling and rising edge of data strobe (dqs) adopted by ddr sdram until the burst length is completed. burst write operation the burst write command is issued by having cs , cas and we low while holding ras high at the rising edge of the clock (clk). the address inputs determine the starting column address. t here is no write latency relative to dqs required for burst w rite cycle. the first data of a burst write cycle must be applied on the dq pins t ds prior to data strobe edge enabled after t dqss from the rising edge of the clock (clk) that the wr ite command is issued. the remaining data inputs must be supplied on each subsequent falling and rising edge of data strobe until the burst length is completed. when the bur st has been finished, any additional da ta supplied to the dq pins will be ignored. note * 1: the specific requirement is that dqs be valid (high or low) on or before this clk edge. the case shown (dqs going fro m high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on t dqss . 01 23 4 5 67 8 command read a nop nop nop nop nop nop nop nop clk cl k cas latency=3 dqs dq's d out0 d out1 d out2 d out3 t rpre t rpst 01 23 4 5 67 8 c ommand nop write a nop nop nop nop nop nop clk clk dqs dq's d in 0 write b d in1 d in2 d in3 t dqss max t wpres *1 *1 *1 d in 0 d in1 d in2 d in3
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 19/48 read interrupted by a read a burst read can be interrupted before completion of the burst by new read command of any bank. when the previous burst is interrupted, the remaining addresses are overridden by the new a ddress with the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command is satisfied. at this point the data from the interrupting read command appears. read to read interval is t ccd (min). read interrupted by a write & burst terminate to interrupt a burst read with a write command, burst terminate command must be asserted to avoi d data contention on the i/o bu s by placing the dq?s (output dr ivers) in a high impedance state. to insure the dq?s are tri-stated one cycle before the beginnin g the write operation, burt stop command must be applied at least ru(cl) clocks [ru mean r ound up to the nearest integer] before the write command. 01 234 5678 command dqs dq's read nop nop nop nop nop d out 0 burst termi nate d in 0 d out 1 d in 1 d in 2 d in 3 clk clk nop write the following functionality establishes how a write command may interrupt a read burst. 1. for write commands interrupting a read burst, a burst terminat e command is required to stop the read burst and tristate the dq bus prior to valid input write data. once the burst te rminate command has been issued, the minimum delay to a write command = ru(cl) [cl is the cas latency and ru means round up to the nearest integer]. 2. it is illegal for a write and burst terminate comm and to interrupt a read with auto precharge command. 01 234 5678 command dqs dq's read a nop nop nop nop nop nop nop d out a 0 read b d out a 1 d out b 2 d out b 3 d out b 0 d out b 1 clk clk t ccd(min) hi -z hi- z
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 20/48 read interrupted by a precharge a burst read operation can be interrupted by precharge of the same bank. the minimum 1 clock is required for the read to precharge intervals. a precharge command to out put disable latency is equivalent to the cas latency. 01 234 5678 command dqs dq's read nop nop nop nop nop nop d out 0 precharge 1t ck nop interrupted by precharge clk clk d out 1 d out 2 d out 3 d out 4 d out 5 d out 6 d out 7 when a burst read command is issued to a ddr sdram, a pr echarge command may be issued to the same bank before the read burst is complete. the following f unctionality determines when a precharge comm and may be given during a read burst and when a new bank activate command may be issued to the same bank. 1. for the earliest possible precharge co mmand without interrupting a read burst, t he precharge command may be given on the rising clock edge which is cl clock cycles bef ore the end of the read burst where cl is the cas latency. a new bank activate command may be issued to the same bank after t rp (ras precharge time). 2. when a precharge command interrupts a read burst operation, the precharge command may be given on the rising clock edge which is cl clock cycles before the last data from the interrupted read burst where cl is the cas latency. once the last data word has been output, the output buffers are tristate d. a new bank activate command may be issued to the same bank after t rp . 3. for a read with auto precharge command, a new bank ac tivate command may be issued to the same bank after t rp where t rp begins on the rising clock edge which is cl clock cycl es before the end of the re ad burst where cl is the cas latency. during read with auto precharge, the initia tion of the internal precharge occurs at the same time as the earliest possible external precharge command would initiate a precharge operation without interrupting the read burst as described in 1 above. 4. for all cases above, t rp is an analog delay that needs to be converted into clock cycles. the number of clock cycles between a precharge command and a new bank activate command to the same bank equals t rp / t ck (where t ck is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. in all cases, a precharge operati on cannot be initiated unless t ras (min) [minimum bank activate to precharge time] has been satisfied. this includes read with auto precharge commands where t ras (min) must still be satisfied such that a read with auto precharge command has the same timing as a read command followed by the earliest possible precharge command which does not interrupt the burst.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 21/48 write interrupted by a write a burst write can be interrupted before comple tion of the burst by a new write command , with the only restriction that the inte rval that separates the commands must be at least one clock cycle. w hen the previous burst is interr upted, the remaining addresses a re overridden by the new address and data will be written into t he device until the programmed bur st length is satisfied. 01 234 5678 command dqs dq's nop nop nop nop nop nop n op d in a0 write a d in a1 d in b2 d in b3 d in b0 d in b1 clk clk 1t ck hi -z hi- z write b
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 22/48 write interrupted by a read & dm a burst write can be interrupted by a read command of any bank. the dq?s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. when the read command is registered, an y residual data from the burst write cy cle must be masked by dm. the delay from the last data to read command (t wtr ) is required to avoid the data contention dram inside. data that are presented on the dq pins before the read command is initiated will actuall y be written to the memory. read command interrupting write can not be issued at the next clock edge of that of write command. 01 234 5678 command dqs dq's dqs dq's nop nop nop nop read nop t dqss(max ) d in0 write t dqss(min) dm clk clk dm nop nop hi-z hi-z t wpres t wtr *5 hi-z hi-z t wtr t wpres *5 d in1 d in2 d in3 d in4 d in5 d in6 d in7 d out0 d out1 d out0 d out1 d in0 d in1 d in2 d in3 d in4 d in5 d in6 d in7 the following functionality established how a read command may inte rrupt a write burst and which input data is not written into the memory. 1. for read commands interrupting a write burst, the minimum writ e to read command delay is 2 clock cycles. the case where the write to read delay is 1 clock cycle is disallowed. 2. for read commands interrupting a write burst, the dm pin must be used to mask the input data words which immediately precede the interrupting read operation and the input data word wh ich immediately follows the interrupting read operation. 3. for all cases of a read interrupting a wr ite, the dq and dqs buses must be released by the driving chip (i.e., the memory co ntroller) in time to allow the buses to turn around befor e the sdram drives them during a read operation. 4. if input write data is masked by the read command, the dqs inputs are ignor ed by the ddr sdram. 5. refer to ?burst write operation?
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 23/48 write interrupted by a precharge & dm a burst write operation can be in terrupted before completion of the burst by a pr echarge of the same bank. random column access is allowed. a write recovery time (t wr ) is required from the last data to precharge command. when precharge command is asserted, any residual data from the burst write cycle must be masked by dm. 01 234 5678 command dqs dq's dqs dq's nop nop nop nop nop d ina0 write a dm clk clk dm precharge a hi-z hi-z t wpres *5 t wr hi-z hi-z t wr nop write b t wpres *5 t dqss(max ) t dqss(min) d ina1 d ina2 d ina3 d ina4 d ina5 d ina6 d ina7 d inb0 d inb0 d inb1 d ina0 d ina1 d ina2 d ina3 d ina4 d ina5 d ina6 d ina7 precharge timing for write operations in dr ams requires enough time to allow ?write recovery? which is the time required by a d ram core to properly store a full ?0? or ?1? level before a precharge operation. for ddr sd ram, a timing parameter, t wr , is used to indicate the required of time between the last valid writ e operation and a precharge command to the same bank. t wr starts on the rising clock edge after the last possible dqs edge that strobed in the last valid and ends on the rising clock e dge that strobes in the precharge command. 1. for the earliest possible precharge command following a write burst without interrupt ing the burst, the minimum time for wri te recovery is defined by t wr . 2. when a precharge command interrupts a wr ite burst operation, the data mask pin, dm, is used to mask input data during the ti me between the last valid write data and the rising clock edge in whic h the precharge command is given. during this time, the dqs input is still required to strobe in the state of dm. the minimum time for write recovery is defined by t wr . 3. for a write with auto precharge command, a new bank activate command may be issued to the same bank after t wr + t rp where t wr + t rp starts on the falling dqs edge t hat strobed in the last valid data and ends on the rising clock edge that strobes in the bank activate commands. during write with auto precharge, the initiation of the internal precharge occurs at the same time as the ea rliest possible external precharge command without interrupt ing the write burst as described in 1 above. 4. in all cases, a precharge oper ation cannot be initiated unless t ras (min) [minimum bank activate to precharge time] has been satisfied. this includes write with auto precharge commands where t ras (min) must still be satisfied such that a write with auto precharge command has the same timing as a write command followed by the earliest possible precharge co mmand which does not interrupt the burst. 5. refer to ?burst write operation?
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 24/48 burst terminate the burst terminate command is initiated by having ras and cas high with cs and we low at the rising edge of the clock (clk). the burst terminate command has the fewest restrictions ma king it the easiest method to use when terminating a burst rea d operation before it has been completed. when the burst terminate command is issued duri ng a burst read cycle, the pair of data and dqs (data strobe) go to a high impedance st ate after a delay which is equal to the cas latency set in the mode register. the burst terminate command, however, is not s upported during a wr ite burst operation. 01 234 5678 command read a nop nop nop nop nop nop nop burst te r m in a te clk clk dqs dq's d out 0 hi-z hi-z the burst read ends after a deley equal to the cas lantency. d out 1 the burst terminate command is a mandatory feature for dd r sdrams. the following f unctionality is required. 1. the bst command may only be issued on t he rising edge of the input clock, clk. 2. bst is only a valid command during read burst. 3. bst during a write burst is undefined and shall not be used. 4. bst applies to all burst lengths. 5. bst is an undefined command during read wi th auto precharge and shall not be used. 6. when terminating a burst read command, the bst command must be issued l bst (?bst latency?) clock cycles before the clock edge at which the output buffers are tristated, where l bst equals the cas latency for read operations. 7. when the burst terminates, the dq and dqs pins are tristated. the bst command is not byte controllable and applies to a ll bits in the dq data word and the (all) dqs pin(s). dm masking the ddr sdram has a data mask function that can be used in conj unction with data write cycle. not read cycle. when the data mask is activated (dm high) during write operation, ddr sdram does not accept t he corresponding data. (dm to data-mask latency is zero) dm must be issued at t he rising or falling edge of data strobe. 01 234 5678 command write nop nop nop nop nop nop nop clk clk nop dqs dq's t dqss dm d in 0 hi-z hi-z mas k ed b y d m =h d in 1 d in 2 d in 3 d in 4 d in 5 d in 6 d in 7 t ds t dh
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 25/48 read with auto precharge if a read with auto precharge command is in itiated, the ddr sdram autom atically enters the precharge operation bl/2 clock later from a read with auto precharge command when t ras (min) is satisfied. if not, the start poi nt of precharge oper ation will be delayed until t ras (min) is satisfied. once the precharge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time (t rp ) has been satisfied. 01 234 56789 command bank a active nop nop nop nop nop nop nop read a auto precharge clk clk dqs dq's cas latency = 2 cas latency = 2.5 d out 0 t rp nop * bank can be reactivated at completion of precharge auto-precharge starts hi-z hi-z t ras (min) d out 1 d out 2 d out 3 dqs dq's d out 0 hi-z hi-z d out 1 d out 2 d out 3 when the read with auto precharge command is issued, new comma nd can be asserted at 4, 5 and 6 respectively as follow. for the same bank for the different bank asserted command 4 5 6 4 5 6 read read illegal illegal legal legal legal read with ap *1 read with ap illegal illegal legal legal legal active illegal illegal illegal legal legal legal precharge legal legal illegal legal legal legal note 1: ap = auto precharge
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 26/48 write with auto precharge if a8 is high when write command is issued, the write with auto- precharge function is performed. any new command to the same bank should not be issued until the internal precharge is complete d. the internal precharge begins at the rising edge of the cl k with the t wr delay after the last data-in. 01 234 5678 command dqs dq's bank a active nop nop nop nop nop nop nop d in 0 write a auto precharge *bank can be reactivated at completion of t rp t wr t rp internal precharge start clk clk d in 1 d in 2 d in 3 at burst read / write with auto precharge, cas interrupt of the same bank is illegal. for the same bank for the different bank asserted command 4 5 6 7 8 4 5 6 7 8 write write write illegal illegal illegal legal legal legal legal legal write with ap *1 write with ap write with ap illegal illegal illegal legal legal legal legal legal read illegal read + dm *2 read+ dm read illegal illegal illegal illegal legal legal read with ap illegal read with ap+ dm read with ap+ dm read with ap illegal illegal illegal illegal legal legal active illegal illegal illegal illegal illegal legal legal legal legal legal precharge illegal illegal illegal illegal illegal legal legal legal legal legal note: 1. ap = auto precharge 2. dm: refer to ?write interrupted by a read & dm?
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 27/48 auto refresh & self refresh auto refresh an auto refresh command is issued by having cs , ras and cas held low with cke and we high at the rising edge of the clock (clk). all banks must be precharged and idle for t rp (min) before the auto refresh command is applied. no control of the external address pins is requires once this cycle has started because of the internal address counter. when the refresh cycle h as completed, all banks will be in the idle state. a delay betw een the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the t rfc (min). a maximum of eight consecutive auto refresh commands (with t rfc (min)) can be posted to any given ddr sdram meaning that the maximum absolute interval between any auto re fresh command and the next auto refresh command is 8 x t refi . command cke = high t rp pre auto refresh cmd t rfc clk clk self refresh a self refresh command is defines by having cs , ras , cas and cke held low with we high at the rising edge of the clock (clk). once the self refresh command is initiated, cke must be held low to keep the device in self refresh mode. during the sel f refresh operation, all inputs except cke ar e ignored. since cke is an sstl_2 input, v ref must be maintained during self refresh. the clock is internally disabled during self refresh operation to reduce power consumption. the self refresh is exited by suppl ying stable clock input before returning cke high, asserting deselec t or nop command and then asserting cke high for longer than t xsrd for locking of dll. command cke t xsnr(min) self refresh auto refresh nop t is clk clk nop nop nop nop nop t is note: after self refresh exit, input an auto refresh command immediately.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 28/48 power down power down is entered when cke is registered low (no accesses can be in progress). if power down occurs when all banks are idle , this mode is referred to as precharge powe r-down; if power down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power down deactivates the i nput and output buffers, excluding clk, clk and cke. in power down mode, cke low must be maintained, and all other input signals are ?don?t ca re?. the minimum power down duration is at least 1 t ck + t is . however, power down duration is limited by t he refresh requirements of the device. the power down state is synchronously exited when cke is r egistered high (along with a nop or deselect command). a valid command may be applied 1 t ck + t is after exit from power down. command cke clk clk precharge read enter precharge power-down mode t is t is t is t is active exit precharge power-down mode enter active power-down mode exit active power-down mode t rp functional truth table truth table ? cke [note 1~4, 6] cke n-1 cke n current state command n action n note l l power down x maintain power down l l self refresh x maintain self refresh 7 l h power down nop or deselect exit power down l h self refresh nop or deselect exit self refresh 5, 7 h l all banks idle nop or deselect precharge power down entry h l bank(s) active nop or deselect active power down entry h l all banks idle auto refresh self refresh entry h h see the truth tables as follow notes: 1. cke n is the logic state of cke at clock edge n; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of ddr sdram immediately prior to clock edge n. 3. command n is the command registered at clock ed ge n, and action n is the result of command n. 4. all states and sequences not shown are illegal or reserved. 5. deselect and nop deselect or nop commands should be issued on any clock edges occurring during the t xsnr or t xsrd period. a minimum of 200 clock cycles is needed before applying any executable command, for the dll to lock. 6. operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the dr am must be powered down and then restarted through the spec ified initialization sequence before normal operation can continue. 7. v ref must be maintained during self refresh operation.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 29/48 truth table ? current state bank n current state cs ras cas we command / action note command to bank n [note 1~6,13] h x x x deselect (nop / continue previous operation) any l h h h no operation (nop / conti nue previous operation) l l h h active (select and activate row) l l l h auto refresh 7 idle l l l l mode register set 7 l h l h read (select column & start read burst) 10 l h l l write (select column & start write burst) 10 row active l l h l precharge (deactivate row in bank or banks) 8 l h l h read (select column & start new read burst) 10 l h l l write (select column & start write burst) 10, 12 l l h l precharge (truncate re ad burst, start precharge) 8 read (auto precharge disabled) l h h l burst terminate 9 l h l h read (select column & start read burst) 10, 11 l h l l write (select column & start new write burst) 10 write (auto precharge disabled) l l h l precharge (truncate writ e burst, start precharge) 8, 11 command to bank m [note 1~3, 6,13~15] h x x x deselect (nop / continue previous operation) any l h h h no operation (nop / c ontinue previous operation) idle x x x x any command allowed to bank m l l h h active (select and activate row) l h l h read (select column & start read burst) 10 l h l l write (select column & start write burst) 10 row activating, active, or precharging l l h l precharge l l h h active (select and activate row) l h l h read (select column & start new read burst) 10 l h l l write (select column & start write burst) 10, 12 read (auto precharge disabled) l l h l precharge l l h h active (select and activate row) l h l h read (select column & start read burst) 10, 11 l h l l write (select column & start new write burst) 10 write (auto precharge disabled) l l h l precharge l l h h active (select and activate row) l h l h read (select column & start new read burst) 3a, 10 l h l l write (select column & start write burst) 3a, 10, 12 read with auto precharge l l h l precharge l l h h active (select and activate row) l h l h read (select column & start read burst) 3a, 10 l h l l write (select column & start new write burst) 3a, 10 write with auto precharge l l h l precharge
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 30/48 notes: 1. this table applies when cken-1 was high and cken is high and after t xsnr or t xsrd has been met (if the previous state was self refresh). 2. this table is bank - specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcdrd or t rcdwr has been met. no data bursts/accesses and no register accesses are in progress. read / write: a read / write burst has been initiat ed, with auto precharge disabled, and has not yet terminated or been terminated. read / write with auto precharge enabled: see following text, notes 3a, 3b: 3a. for devices which do not support the optional ?conc urrent auto precharge? feature, the read with auto precharge enabled or write with auto precharge en abled states can each be brok en into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible precharge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access period starts with registration of the co mmand and ends where the precharge period (or t rp ) begins. during the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, active, precharge, read and write commands to t he other bank may be applied; during the access period, only active and precharge commands to the ot her bank may be applied. in either case, all other related limitations apply (e.g., contention betwe en read data and write data must be avoided). 3b. for devices which do support the optional ?concurrent aut o precharge? feature, a re ad with auto precharge enabled, or a write with auto precharge enabled, may be followed by any command to the other banks, as long as that command does not interrupt the read or write data transfer, an d all other related limitations apply (e.g., contention between read data and write data must be avoided.) 4. the following states must not be interrupted by a comma nd issued to the same bank. deselect or nop commands, or allowable commands to the other bank should be issued on an y clock edge occurring during these states. allowable commands to the other bank are determin ed by its current state and truth table. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcdrd or t rcdwr is met. once t rcdrd or t rcdwr is met, the bank will be in the ?row active? state. read/ write with auto - precharge enabled: starts with registration of a r ead / write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any ex ecutable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rfc is met, the ddr sdram will be in the ?all banks idle? state. accessing mode register: starts with registrati on of a mode register set command and ends when t mrd has been met. once t mrd is met, the ddr sdram will be in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank - specific; requires that all ban ks are idle and no bursts are in progress. 8. may or may not be bank - specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. not bank - specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the co mmand/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking. 12. a write command may be applied after the completion of t he read burst; otherwise, a burst terminate must be used to end the read prior to asserting a write command, 13. operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the d ram must be powered down and then restarted through the spec ified initialization sequence before normal operation can continue. 14. auto refresh and mode register set commands may only be issued when all banks are idle. 15. a burst terminate command cannot be issued to another bank; it applies to the bank repres ented by the current state only.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 31/48 timing diagram basic timing (setup, hold and access time @ bl=4, cl=2) cke cs ras cas ba0,ba1 addr (a0~an) we dqs dq 01 234 5678910 high dm command a 8 /ap baa bab cb db0 db1 db3 db2 t ck t is t ih t dqsck t rpre t dqsck qa0 qa1 qa2 qa3 t rpst hi-z t dqss t wpre t dqsh t dqsl t ds t dh t ds t dh t wpst hi-z hi-z read write clk clk t cl t ch t ck t cl t ch baa ra ca ra active t dqsq t qh :don?tcare hi-z t lz t ac t hz t wpres 10122b32r.b
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 32/48 multi bank interleaving read (@ bl=4, cl=2) cke cs ras cas ba0,ba1 we dqs dq 01 234 5678910 high dm command a 8 /ap addr (a0~an) baa qb0 qb1 qb3 qb2 active bab baa bab ra rb ra ca cb qa0 qa1 qa3 qa2 active read read rb clk clk t ccd : don?t care 10122b32r.b1 t rcdrd t rrd
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 33/48 multi bank interleaving write (@ bl=4) cke cs ras cas ba0,ba1 we dqs dq 01 234 5678910 high dm command a 8 /ap addr (a0~an) baa db0 db1 db3 db2 active bab baa bab ra ca cb da0 da1 da3 da2 active write t rcdwr write t rrd t ccd rb clk clk ra rb :don?tcare 10122b32r.b1 t rcdwr
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 34/48 read with auto precharge (@ bl=8) cke cs ras cas ba0,ba1 we dqs(cl=2) dq(cl=2) 01 234 5678910 high dm command a 8 /ap addr (a0~an) baa qa4 qa5 qa7 qa6 baa t rp qa0 qa1 qa3 qa2 active read ca auto precharge start note1 clk clk ra dqs(cl=2.5) dq(cl=2.5) qa4 qa5 qa7 qa6 qa0 qa1 qa3 qa2 :don?tcare 10122b32r.b note: 1. the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of another activated bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same/another bank is illegal.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 35/48 write with auto precharge (@ bl=8) cke cs ras cas ba0,ba1 we dqs dq 01 234 5678910 high dm command a 8 /ap addr (a0~an) baa da4 da5 da7 da6 t rp da0 da1 da3 da2 active write ca auto precharge start note1 baa ra t wr clk clk t dal :don?tcare 10122b32r.b note: 1. the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of another activated bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same/another bank is illegal.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 36/48 write followed by precharge (@ bl=4) cke cs ras cas ba0,ba1 we dqs dq 01 234 5678910 high dm command a 8 /ap addr (a0~an) baa baa t wr da0 da1 da3 da2 pre charge write ca clk clk :don?tcare 10122b32r.b
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 37/48 write interrupted by precharge & dm (@ bl=8) cke cs ras cas ba0,ba1 we dqs dq 01 234 012345 high dm command a 8 /ap addr (a0~an) baa baa da0 da1 da3 da2 pre charge write write write ca clk clk bab bac cb cc db0 db1 dc1 dc0 dc3 dc2 t ccd da4 da5 da7 da6 :don?tcare 10122b32r.b
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 38/48 write interrupted by a read (@ bl=8, cl=2) cke cs ras cas ba0,ba1 we dqs dq 01 234 5678910 high dm command baa t wtr da0 da1 da3 da2 write read ca clk clk bab cb da5 da4 qb1 qb3 qb2 qb4 qb5 a 8 /ap addr (a0~an) qb6 qb0 qb6 :don?tcare 10122b32r.b
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 39/48 read interrupted by precharge (@ bl=8) cke cs ras cas ba0,ba1 we dqs(cl=2) dq(cl=2) 01 234 5678910 high command a 8 /ap addr (a0~an) baa qa0 qa1 read bab ca pre charge clk clk qa2 qa3 qa4 qa5 dm 2t ck valid dqs(cl=2.5) dq(cl=2.5) qa0 qa1 qa2 qa3 qa4 qa5 2.5 t ck valid :don?tcare 10122b32r.b when a burst read command is issued to a ddr sdram, a precharge command may be issued to the same bank before the read burst is complete. the following functionality determines when a precharge command may be given during a read burst and when a new bank activate command may be issued to the same bank. 1. for the earliest possible precharge command without interr upting a read burst, the precharge command may be given on the rising clock edge which is cl clock cycles before the end of the read burst where cl is the cas latency. a new bank activate command may be issued to the same bank after t rp (ras precharge time). 2. when a precharge command interrupts a read burst operation, the precharge command may be given on the rising clock edge which is cl clock cycles before the last data from the interru pted read burst where cl is the cas latency. once the last data word has been output, the output buffers are tri-stated. a new bank activate command may be issued to the same bank after t rp .
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 40/48 read interrupted by a write & burst terminate (@ bl=8, cl=2) cke cs ras cas ba0,ba1 we dqs dq 01 234 5678910 high dm command baa qa0 qa1 read db0 db5 db1 db4 db3 db2 db6 bab cb burst te rm i n a t e write db7 clk clk a 8 /ap addr (a0~an) ca : don?t care 10122b32r.b
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 41/48 read interrupted by a read (@ bl=8, cl=2) cke cs ras cas ba0,ba1 we dqs dq 01 234 5678910 high dm command a 8 /ap addr (a0~an) baa qb2 qb3 qb5 qb4 qa0 qa1 qb1 qb0 read ca clk clk bab cb qb7 qb6 read t ccd :don?tcare 10122b32r.b
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 42/48 dm function (@ bl=8) only for write cke cs ras cas ba0,ba1 we dqs dq 01 234 5678910 high dm command a 8 /ap addr (a0~an) baa da4 da5 da7 da6 da0 da1 da3 da2 write ca clk clk :don?tcare 10122b32r.b
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 43/48 power up & initialization sequence (based on ddr400) v ddq v ref a0-a7 a9-an power-up: vdd and clk stable ba0, ba1 extended mode register set command dm dqs t mrd t mrd 200 cycles of clk** load mode register reset dll (with a8=h) load mode register (with a8=l) v dd a8 t=200us v tt (system*) t vdt >=0 clk clk cke nop t ch t cl t ck t is t ih pre emrs mrs pre ar ar mrs act t ih t is code t ih t is lvcoms low level code code ra t ih t is code code code ra ba0=l, ba1=l ba t ih t is t ih t is ba0=l, ba1=l high-z dq high-z t rp t rfc t mrd all banks all banks t rfc ba0=h, ba1=l t ih t is :don?tcare 10122b32r.b notes: * = v tt is not applied directly to the device, however t vtd must be greater than or equal to zero to avoid device latch-up. ** = t mrd is required before any command can be applied, and 200 cycles of clk are required before an executable command can be applied. the two auto refresh commands may be mo ved to follow the first mrs but precede the second precharge all command.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 44/48 mode register set cke cs ras cas ba0,ba1 we ds dq 01 234 5678910 high dqs a 8 /ap addr (a0~an) t rp t mrd clk clk high-z high-z precharge command all bank mode register set command any command address key : don?t care 10122b32r.b note: power & clock must be stable for 200us before precharge all banks.
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 45/48 simplified state diagram preall = precharge all banks mrs = mode register set emrs = extended mode register set refs = enter self refresh refsx = exit self refresh refa = auto refresh ckel = enter power down ckeh = exit power down act = active write a = write with autoprecharge read a = read with autoprecharge pre = precharge
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 46/48 packing dimensions 144-ball fbga ddr dram (12x12mm) symbol dimension in mm dimension in inch min norm max min norm max a 1.14 1.40 0.049 0.055 a1 0.30 0.35 0.40 0.012 0.014 0.016 b 0.40 0.45 0.50 0.016 0.018 0.020 d 11.90 12.00 12. 10 0.469 0.472 0.476 e 11.90 12.00 12. 10 0.469 0.472 0.476 d1 8.80 0.346 e1 8.80 0.346 e 0.80 0.031 aaa 0.10 0.004 bbb 0.10 0.004 ddd 0.12 0.005 eee 0.15 0.004 fff 0.08 0.006 md/me 12/12 12/12
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 47/48 revision history revision date description 0.1 2009.12.10 original 0.2 2009.12.23 delete cas latency 4 1.0 2010.03.05 delete ?preliminary? 1.1 2010.03.29 add package descrip tion into ball configuration 1.2 2010.05.27 1. modify the specification of t dqsq for -5 2. distribute t rcd into t rcdrd and t rcdwr 1.3 2011.08.09 1. add operating ambient temper ature into absolute maximum ratings 2. correct active/precharge power down mode of command truth table
esmt m13s128324a (2m) elite semiconductor memory technology inc. publication date : aug. 2011 revision : 1.3 48/48 important notice all rights reserved. no part of this document may be reproduc ed or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the product s or specification in this document without notice. the information contained herein is presen ted only as a guide or examples for the application of our products. no res ponsibility is assumed by esmt for any infringement of patents, copyrights, or ot her intellectual propert y rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of esmt or others. a ny semiconductor devices may have inhere ntly a certain rate of failure. to minimize risks associated with custom er's application, adeq uate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or caus e physical injury or property damage. if products described here are to be used for such kinds of applicat ion, purchaser must do its own quality assurance test ing appropriate to such applications.

▲Up To Search▲

Price & Availability of M13S128324A-2M

	To Download M13S128324A-2M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .